AMD RDNA 5 Leak Points to Stronger Shader Throughput via Dual-Issue

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A new RDNA 5 compiler trail suggests AMD is expanding dual-issue Wave32 support, aiming to raise real shader throughput in FP32-heavy gaming workloads.

Quick Report

A new compiler level trail suggests AMD is broadening dual-issue execution behavior for its upcoming RDNA 5 generation, with changes that could improve practical shader throughput in games. The report points to GFX1310 updates that let more vector and fused multiply-add style instructions issue across X and Y ALU lanes in Wave32 mode.

If these ISA and compiler changes translate cleanly to shipping drivers, RDNA 5 could close part of the long standing gap between theoretical and real world FP32 performance seen in prior implementations. The story still sits in pre launch territory, but it adds another signal that AMD is targeting heavier neural rendering, upscaling, frame generation, and ray tracing era workloads with a stronger shader execution path.

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