AMD Reworks EPYC Venice Packaging With Zen 6 for Denser AI Racks

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AMD EPYC Venice with Zen 6 debuts a radical package: dual 4 nm server I/O dies, eight 2 nm CCDs, 256 cores/512 threads, 16-channel DDR5, higher PCIe/CXL.

Quick Report

AMD unveiled EPYC Venice with Zen 6 at CES 2026, showing a radical package redesign aimed at dense AI racks. The chip places two slender server I/O dies (sIODs) on 4 nm at the center, flanked by up to eight 2 nm compute chiplets (CCDs), enabling a 256-core/512-thread configuration per socket with a 16-channel DDR5 memory interface and significantly expanded PCIe/CXL connectivity.

The company showcased “Helios” racks pairing one EPYC Venice CPU with four MI455X GPUs per node, highlighting the platform's interconnect bandwidth goals. Each CCD reportedly carries 32 Zen 6 cores, while the dual sIOD layout disaggregates I/O for higher lane counts and fabric scalability. AMD's Venice design focuses on memory bandwidth (16 channels, 32 sub-channels) and broad device connectivity for AI accelerators, DPUs, and 800G NICs.

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Source(s)

  • TPU