Intel Demos Packaging for 16 Compute Dies and 24 HBM5 Modules

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Intel demos packaging for up to 16 compute dies and 24 HBM5 modules, using Foveros 3D, EMIB-T, and 18A/14A nodes for AI and HPC.

Quick Report

Intel has demonstrated a next-generation packaging technology capable of integrating up to 16 compute dies and 24 HBM5 memory modules in a single package.

This approach uses Foveros 3D stacking, EMIB-T interconnects, and advanced 18A/14A nodes to scale silicon beyond reticle limits, supporting massive AI and HPC workloads. The design features base dies with backside power delivery and SRAM, topped with compute tiles using second-gen RibbonFET transistors. Intel's roadmap includes support for all HBM standards and even envisions 5,000 W GPUs by 2027, positioning its packaging as a direct competitor to TSMC's CoWoS for external foundry customers.

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Source(s)

  • TPU