Cadence Tapes Out 64G UCIe IP on TSMC N3P, Pushing Chiplet Interconnects Forward

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Cadence tapes out 64G UCIe IP on TSMC N3P, enabling high-speed, energy-efficient chiplet connectivity for AI and HPC.

Quick Report

Cadence has successfully taped out its third-generation Universal Chiplet Interconnect Express (UCIe) IP, achieving 64 Gbps per-lane speeds on TSMC's advanced N3P process. This milestone enables ultra-high bandwidth density and energy-efficient die-to-die communication, targeting AI, HPC, and data center platforms.

The new UCIe IP supports a wide range of protocols—including AXI, CXS, CHI-C2C, PCIe, and CXL—and features advanced error correction, lane margining, and diagnostic tools for robust operation. With bandwidth density reaching up to 21.08 Tbps/mm in advanced packages, Cadence's solution is designed for scalable, multi-vendor chiplet ecosystems. Self-calibrating hardware and streamlined clocking further simplify integration for SoC designers.

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Source(s)

  • TPU