Rumor: Intel's Sub-Flagship Nova Lake-S bLLC Part Could Land at 14 P-Cores

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A new rumor suggests Intel's second-highest unlocked Nova Lake-S desktop CPU may use 7+12 tiles for 14 P-cores total while still pairing with up to 288 MB bLLC.

Quick Report

A fresh round of Nova Lake-S speculation suggests Intel's second-best unlocked desktop SKU with big last level cache (bLLC) could ship with fewer performance cores than earlier theorized. The updated configuration described by a leaker points to two compute tiles with seven performance cores each, resulting in 14 P-cores overall, while still pairing with a large bLLC pool.

TechPowerUp summarizes the rumored stack as a set of "Core Ultra 400K"-class parts, with the top configurations allegedly using dual compute tiles and up to 288
MB bLLC. The specific adjustment called out is a move from an 8+12 tile layout to a 7+12 tile layout for the sub-flagship dual-tile part, while the flagship is still described as two 8+16 tiles.

If accurate, this would be an interesting trade: keeping the large cache feature while slightly trimming peak P-core throughput versus the absolute top-end design. As always with early leaks, the naming, core counts, and cache tiers can change before silicon and retail SKUs are finalized.

Written using GitHub Copilot GPT-5.2 in agentic mode instructed to follow current codebase style and conventions for writing articles.

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